I have a first-generation AMD Threadripper (1950x) on an Asus Zenith Extreme motherboard. I had one PC3000 64GB kit suited for Intel timings, that I had tuned to stability. I thought I was getting a matching kit, but it turns out to be 64GB of PC3200 at Intel timings. Determined to make it work, I turned to AI for some actually helpful advice:

USER

I have two mismatched RAM kits in an AMD Threadripper 1950X that I need to run as fast and stable as possible.

Kit one: PC3200 CAS Latency 16 RAS# to CAS# 20 RAS# Precharge 20 tRAS 38 tRC 58

Kit two: PC3000 CAS Latency 15 RAS# to CAS# 17 RAS# Precharge 17 tRAS 35 tRC 52

My BIOS has the following timing options: CAS# Latency RAS# to CAS# Delay Read RAS# to CAS# Delay Write RAS# PRE Time RAS# ACT Time Trc TrrdS

Please suggest settings that could satisfy both kits while running as fast as possible. Provide suggestions of how to adjust the values if unstable.

ASSISTANT

Short answer first: with mixed kits on a first‑gen Threadripper (1950X), aim for DDR4‑2933 first, using the looser kit’s primary timings as your baseline, then tighten carefully. 3000 MT/s may work; 3200 MT/s usually gets touchy on Zen 1 with mixed modules, especially with more than four DIMMs.

Suggested starting profile (fast but conservative)

  • Memory frequency: 2933 MT/s
  • DRAM Voltage: 1.35 V
  • SOC Voltage: 1.05–1.10 V to start (you can go up to ~1.15–1.16 V if needed)
  • CAS# Latency (tCL): 16
  • RAS# to CAS# Delay Read (tRCDRD): 20
  • RAS# to CAS# Delay Write (tRCDWR): 20
  • RAS# PRE Time (tRP): 20
  • RAS# ACT Time (tRAS): 38
  • Trc (tRC): 58
  • TrrdS: 6 (or leave on Auto; if you must set it and see instability, try 7–8)

Why these values

  • They match or slightly relax the looser kit (16-20-20-38, tRC 58), which gives both kits a fair chance to train.
  • tRC set to at least tRAS + tRP (38 + 20 = 58) maintains stability margin.

If it’s fully stable, ways to go faster

  • Try raising frequency to 3000 MT/s with the same timings/voltages.
  • Or keep 2933 MT/s and tighten one step at a time:
    • tRCDRD/tRCDWR: 19
    • tRP: 19
    • tRAS: 36
    • tRC: 56
  • If those hold, you can attempt CL15 at 2933 (15-19-19-36, tRC 55–56), but expect diminishing returns vs effort.

If you get instability (POST loops, MemTest errors, app crashes)

  • Voltages (small, incremental changes)
    • DRAM Voltage: 1.36 → 1.37 → 1.38 V, watching temps.
    • SOC Voltage: 1.10 → 1.12 → up to ~1.15–1.16 V if needed. Many heavy-population TR systems require ~1.16 V SoC for higher memory clocks [1].
  • Timings (relax in small steps)
    • tRCDRD/tRCDWR: 21
    • tRP: 21
    • tRAS: 40
    • tRC: 60–64 (ensure tRC ≥ tRAS + tRP)
    • TrrdS: 7–8 if you set it manually.
  • Frequency
    • Drop to 2866 MT/s if 2933/3000 remain flaky even after minor voltage bumps. On 1950X with lots of DIMMs, ~2866–2933 is often the practical ceiling without aggressive voltages [1].
  • Boot training help
    • If you see cold‑boot or training failures, set DRAM Boot/Start Voltage to ~1.40 V (if your board offers it) to aid training, then let it run 1.35–1.38 V in‑OS [1].
  • Command rate / Gear Down (only if available on your board)
    • Enable Gear Down Mode to keep effective 1T training; if still unstable, try CR 2T.

Stability testing (recommended)

  • Quick sanity: multiple passes of a RAM test (HCI Memtest/Karhu/TM5).
  • Heavier load specific to Ryzen/Threadripper:
    • Prime95 v28.10, Torture Test > Custom > Min FFT 128K, Max FFT 128K, “in‑place” checked; run ≥30–60 minutes to vet memory controller stability as recommended by experienced Ryzen tuners [8].
  • Then stress your real workloads (games, rendering, compiles) for several hours.

Notes and expectations for 1950X

  • Mixing kits (ICs, SPD, and binning) lowers headroom. Don’t be surprised if 3000 MT/s is your stable top unless you add voltage and relax timings.
  • Community experience shows 2866–2933 often being the “easy” zone on 1950X with larger DIMM counts; moving beyond can require 1.36–1.40 V DRAM and ~1.15–1.16 V SoC, plus careful training/boot voltage tweaks [1].

References from the field

  • A 1950X user with 128 GB found 2933 MT/s difficult even with higher DRAM voltage; they ran ~2866 MT/s stable with 1.3675 V DRAM and ~1.165 V SoC, and used higher DRAM boot voltage to improve training [1].
  • For stress testing, Prime95 v28.10 128K in‑place is a known-good detector of Ryzen memory/IMC instability; newer versions sometimes don’t stress it the same way [8].

If you share how many DIMMs you’re running and your exact motherboard, I can suggest secondary/tertiary timings (e.g., tRRDL, tFAW, tRFC) and board-specific training options for a little more headroom.

USER

Why does the system sometimes ‘false start’ and spin up and shut down several times before POSTing?

ASSISTANT

Short version: those “false starts” are almost always DRAM training. On Ryzen/Threadripper, the motherboard may power‑cycle a few times on a cold boot while it tries different memory parameters. With mixed kits and higher clocks, training often needs extra retries, so you see multiple spin‑ups before POST.

What you can do to reduce it

  • Enable the board’s “Memory Context Restore” or “Memory Fast Boot” option so it doesn’t do a full training on every boot. On ASUS boards this stops the long yellow‑LED training each time and still runs your rated speed [4].
  • Give the memory controller more help at cold boot:
    • Set DRAM Boot/Start Voltage a bit higher (e.g., ~1.40 V for training) while keeping run voltage ~1.35–1.38 V. This often fixes foul/looping POST with heavily populated or mixed DIMMs on TR [2].
    • Bump SoC voltage slightly (around 1.05–1.15 V) and keep frequency to a realistic target (2866–2933 MT/s is a common sweet spot on 1950X with lots of DIMMs) [2].
    • If available, enable Gear Down Mode or use 2T command rate to ease training.
  • Sanity‑check the RAM: test each stick/slot. A marginal DIMM can cause repeated power‑cycling before POST; replacing the bad stick/kit resolved this exact symptom for one TR/X399 user [3].
  • Avoid mixing kits if you can. Board vendors recommend using matched, QVL‑listed kits because mixed SPD/ICs increase training difficulty and failure risk [5].

Why it’s worse on cold boot

  • The controller must initialize from scratch (no prior trained values cached), so boards may try several parameter sets and reset between attempts until one works. Disabling training‑skip features (or pushing tight/overclocked settings) forces this to happen every time [4].